1. Field of the Invention
The present invention relates to a drive unit for transferring CCD charge, and more particularly to a reduction in the number of terminals between a timing signal generating circuit and the vertical driver of a solid-state image pickup element.
2. Description of the Related Art
FIG. 4 is a block diagram of an essential part of an image pickup unit including a drive unit for transferring CCD charge. As shown in this drawing, a solid-state image pickup element (e.g. a CCD image sensor) 10 accumulates signal charges for each pixel according to the incident luminous energy.
A timing signal generating circuit 12 supplies timing signals Vsig and Hsig to a vertical driver 14 and a horizontal driver 16, respectively. The vertical driver 14 generates vertical drive pulses Vdr containing read pulses and vertical transfer pulses according to the entered timing signal Vsig, and supplies them to the vertical CCD shift register of the CCD image sensor 10. The horizontal driver 16 generates horizontal drive pulses Hdr according to the entered timing signal Hsig, and supplies them to the horizontal CCD shift register of the CCD image sensor 10.
The signal charges accumulated in the CCD image sensor 10 are successively read out as CCD output signals, each of a voltage matching a signal charge, according to the vertical drive pulses Vdr applied from the vertical (V) driver 14 and the horizontal drive pulses Hdr applied from the horizontal driver 16.
The CCD output signals read out of the CCD image sensor 10 are applied to an analog front end (AFE) 18 via a capacitor C. The AFE 18, as shown in FIG. 5, has a CDS circuit 18A, an amplifier 18B and an A/D converter 18C among other elements. The CDS circuit 18A subjects entered CCD signals to correlation double sampling according to CDS pulses supplied from the timing signal generating circuit 12. The signals processed by the CDS circuit 18A, after being subjected to gain control by the amplifier 18B, is supplied to the A/D converter 18C. The A/D converter 18C converts the input signals, on a pixel-by-pixel basis, according to AD pulses supplied from the timing signal generating circuit 12.
Digital picture signals Asig, having undergone pre-treatments including analog processing and A/D conversion by the AFE 18 are supplied as parallel data to a signal processing circuit 20 via a plurality of signal lines 19. The signal processing circuit 20 has a white balance circuit, a gamma correction circuit, a YC processing circuit and a compression-expansion circuit among other elements. After subjecting the picture signals Asig entered from the AFE 18 to digital processing in various manners, the signal processing circuit 20 records the processed signals on a storage medium (not shown).
FIG. 6 shows the conventional timing signal generating circuit 12 and the conventional V driver 14. As illustrated in the drawing, the timing signal generating circuit 12 supplies timing signals XV1 to XV4 for vertical transfer pulses and timing signals XTG1A, XTG1B, XTG3A and XTG3B for read pulses to the V driver 14 via a total of eight signal lines. Incidentally, its output actually includes power and SUB control signals in addition to these timing signals.
FIG. 7 is a timing chart showing an example of the timing signals XV1 to XV4 for the vertical transfer pulses and timing signals XTG1A, XTG1B, XTG3A and XTG3B for read pulses. FIG. 7 illustrates a case in which electric charges accumulated in a light receiving section matching a transfer gate TG1A (not shown) of the CCD 10 are read out to a vertical transfer path, and these read-out charges are transferred to a horizontal transfer path.
As shown in FIG. 7, when electric charges accumulated in the light receiving section matching the transfer gate TG1A are to be read out to the vertical transfer path, the timing signal XTG1A for read pulses is at an L level only during its read period T1, and other timing signals XTG1B, XTG3A and XTG3B are at an H level. In this period, the timing signal XV1 for vertical transfer pulses is at the L level only during a period T2 including the L level period T1 of the timing signal XTG1A, when the timing signals XV2 and XV3 are at the L level and the timing signal XV4 is at the H level.
On the other hand, when these read-out charges are to be transferred to the horizontal transfer path, the timing signals XV1 to XV4 for vertical transfer pulses are shaped into a pulse waveform for four-phase driving of the vertical transfer path for the transferring, and all of the timing signals XTG1A, XTG1B, XTG3A and XTG3B for read pulses are then at the H level.
Referring back to FIG. 6, the V driver 14 has six drivers 14-1 to 14-6 for entering the timing signals XV1 to XV4 for the vertical transfer pulses and the timing signals XTG1A, XTG1B, XTG3A and XTG3B for read pulses. The drivers 14-1, 14-2, 14-4 and 14-5 supply one of three values (VH, VM and VL) according to the state of two inputs, while the drivers 14-3 and 14-6 supply one of two values (VM and VL) according to the state of one input.
FIG. 8 illustrates the output signals (vertical drive pulses V1A, V1B, V2, V3A, V3B and V4) of the six drivers 14-1 to 14-6 into which the timing signals XV1 to XV4 for vertical transfer pulses and the timing signals XTG1A, XTG1B, XTG3A and XTG3B for read pulses shown in FIG. 7 are to be entered.
As is well known, by applying a voltage VH, which is even higher than the voltage VM at the time of transfer, to an electrode matching the transfer gate of the CCD, charges accumulated in the light receiving section matching that transfer gate are read out to the vertical transfer path.
While the image pickup unit shown in FIG. 4 is integrated by providing the timing signal generating circuit 12 in the same semiconductor integrated circuit (IC) 22 as the AFE 18, it is necessary to provide in the IC 22 a group of terminals 26 for sending the timing signals Hsig and Vsig among others to circuits outward from the timing signal generating circuit 12 (the V driver 14 and the H driver 16), entailing the problem of an increased number of IC terminals.
In order to solve this problem, Japanese Patent Application No. 2000-246969 (which was, at the time the present invention was made, not published, not publically known, and assigned to the same assignee to which the present invention was subject to an obligation of assignment) proposes a drive unit for transferring CCD charge, in which the timing signal Vsig is encoded with a view to reducing the number of terminals (the number of signal lines) for the timing signal generating circuit and the V driver.
However, the drive unit for transferring CCD charge in Japanese Patent Application No. 2000-246969 requires on-chip arrangement on the V driver side of a decoder for decoding the encoded timing signal, inviting the problem of an enlarged chip size. It is also necessary to mount on the timing signal generating circuit side a new encoder for encoding the timing signal, which means a factor to push up the cost.